1. Field of the Invention
The present invention relates to a switching output circuit including a high-side transistor and a low-side transistor connected in a push-pull manner.
2. Description of the Related Art
Driving circuits for inverters configured to drive a switching regulator or a discharge lamp, or driving circuits for a motor, include a switching output circuit such as a half-bridge circuit, an H-bridge circuit, or the like. The switching output circuit includes a high-side transistor and a low-side transistor connected in series between a power supply terminal and a ground terminal. With such an arrangement, the high-side transistor and the low-side transistor are switched on and off in a complementary manner. The switching output circuit controls electric power to be supplied to a load or the like, by controlling the ON time of each transistor.
Such a switching output circuit has a problem in that, if the high-side transistor and the low-side transistor are switched on at the same time, shoot-through current flows from the power supply terminal to the ground terminal. In order to solve this problem, in general, with such a switching output circuit, a period is established in which both the high-side transistor and the low-side transistor are set to the OFF state (which will also be referred to as “dead time”), thereby preventing these two transistors from being switched on at the same time.
Related Art Documents
    [Patent Documents]    [Patent Document 1]
Japanese Patent Application Laid Open No. H8-84057
With a circuit described in Patent document 1, the timing at which the high-side transistor is switched on and the timing at which the low-side transistor is switched on are delayed so as to prevent shoot-through current.
Specifically, the following steps are executed.
1. High-side transistor control operation The signal (edge) used as an instruction to switch off the low-side transistor is delayed by a certain period Td. A logical operation is performed on the signal thus delayed and a signal used as an instruction to switch on the high-side transistor, and the high-side transistor is driven according to the signal obtained by means of the logical operation.
2.Low-side transistor control operation
A signal used as an instruction to switch off the low-side transistor is delayed. A logical operation is performed on the signal thus delayed and the signal used as an instruction to switch on the high-side transistor, and the low-side transistor is driven according to the signal obtained by means of the logical operation.
With such a method, the dead time is determined by the delay time Td. In general, the risk of shoot-through current can be reduced by increasing the dead time. However, such a method has a problem as follows. That is to say, in a case in which the switching output circuit is connected to an inductive load such as a coil, during the dead time, the inductive current that occurs at the coil flows through the body diode formed at each transistor that is in the OFF state. This increases current loss, which reduces the efficiency. Conversely, in a case in which the dead time is reduced, there is an increase in the period in which the inductive current that occurs at the coil flows through the channel of each transistor, and does not flow through the body diode thereof. This increases the circuit efficiency. However, such an arrangement leads to an increased risk of shoot-through current.
An arrangement in which the delay time Td is obtained using the CR time constant has a problem in that, in a case in which the power supply voltage for the circuit fluctuates, the delay time fluctuates, leading to fluctuation in the dead time. This problem can be solved by setting a margin for the delay time Td. However, it is not easy to design the required margin. Furthermore, such a margin can become a primary cause of circuit efficiency degradation. Moreover, in a case in which the high-side transistor and the low-side transistor are switched on and off with a high speed, there is a need to reduce the dead time. Accordingly, it is more difficult to design the delay time Td for such an arrangement.